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Boxcar averager
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Boxcar averager : ウィキペディア英語版
Boxcar averager
A boxcar averager (alternative names are gated integrator and boxcar integrator) is an electronic test instrument that integrates the signal input voltage after a defined waiting time (trigger delay) over a specified period of time (gate width) and then average over multiple integration results (samples). The following block diagram shows the main components and signal pathways:
Block diagram of boxcar averager.
The main purpose of this measurement technique is to improve signal to noise ratio in pulsed experiments with often low duty cycle by the following three mechanisms
# signal integration acts as a first averaging step that strongly suppresses noise components with a frequency of the reciprocal gate width and higher
# time-domain based selection of signal parts that actually carry information of interest and neglect of all signal parts where only noise is present
# averaging over a defined number of periods provides low-pass filtering and convenient adjustment of time resolution
Timing diagram of a boxcar averager.
Similar to lock-in amplifier boxcar averagers are mostly used for the analysis of periodic signals. Whereas the lock-in can be understood as sophisticated band pass filters with adjustable center frequency and bandwidth, the boxcar averager allows to define the signal of interest and resulting time resolution mostly in the time domain.
== Principle of operation ==

Classically the boxcar operation is defined by a trigger delay, a gate width and the number of trigger events, i.e. samples, that are averaged over in the buffer.
The principle of operation can be understood as a two-step process:
# signal integration over the desired gate width
# averaging the integrated signal over a defined amount of periods/trigger events
Considering a simple implementation of the core circuitry looks like regular RC low pass filter that can be gated by a switch S:
Provided the filter time constant τ = RC is set to sufficiently large values with respect to the gate width, the output voltage is to a good approximation the integral of the input signal with a signal bandwidth of B = 1/(4RC). The output of this filter can then be subjected to another analog circuit for subsequent averaging. After each trigger event this sampling circuit has to be set back before receiving the next pulse. The time it takes for this reset is one of the major speed limitations for analog implementations, where maximum trigger rates of a few 10 kHz are typical even though the gate width itself can be as low as a few ten picoseconds and delay is set to zero.

抄文引用元・出典: フリー百科事典『 ウィキペディア(Wikipedia)
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